Chemical etch solution and technique for imaging a device&#39;s shallow junction profile

ABSTRACT

The present invention provides, in one aspect, a method of imaging a microelectronics device  100 . The method comprises cleaning, when contaminants are preset, a sample of a microelectronics device  100  to be imaged with a first solution comprising hydrofluoric acid, an inorganic acid and water, exposing the sample to a second solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the second solution forms a contrast between different regions within the sample, and producing an image of the contrasted sample.

This application is a divisional of application Ser. No. 11/028,833,filed Jan. 4, 2005.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed in general to the manufacture ofsemiconductor devices, and, more specifically, to a chemical etchsolution and technique for imaging device's shallow junction profile.

BACKGROUND OF THE INVENTION

The continuing push to produce faster microelectronic devices with lowerpower consumption has resulted in the miniaturization of such devices.In particular, smaller gate length and channel lengths are conducive tothe low voltage and faster operation of transistor devices, such ascomplementary metal oxide semiconductor (CMOS) transistors. However,with shrinking process geometries, a number of new design problemsarise.

For instance, as gate dimensions are reduced, it has become necessary toadjust and better control the dimensions of the channel and dopedregions of the substrate that are associated with the gate. This isnecessary to prevent a number of short channel effects such as,threshold voltage variation, drain induced barrier lowering (DIBL),punch-through, leakage currents, hot carrier injection, and mobilitydegradation.

Consider, for instance, the dimensions of shallow junctions and pocketregion structures. Shallow junctions, also referred to as source drainextensions, or light or medium-doped drain (LDD and MDD, respectively)regions, are implanted as extensions to the larger and more heavilydoped source and drain regions, to reduce hot carrier injection-induceddamage to gate dielectric layers and improve short channel effects. Hotcarriers, electrons with higher than average energy, form because of thestronger electric fields produced in small transistor device geometries.Shallow junctions, implanted before sidewall formation and source anddrain implantation, provide a doping gradient between the source anddrain regions and the channel. The lowered electric field in thevicinity of the channel region of such devices reduces the formation ofhot carriers.

Sub-0.1 micron transistor devices are also highly susceptible to leakagecurrents, or punch-through, when the transistor is off. These conditionscan arise when the shallow junctions and the source/drains are notproperly formed. Thus, leakage currents can be reduced if the shallowjunctions are formed with well-defined boundaries, as exemplified by anabrupt decrease in dopant concentration, to support low-voltageoperation of the transistor and to define the width of the channelregion of the transistor.

Unfortunately, however, it can be very difficult to ascertain anyirregularities in these shallow junctions or source/drain areas usingstandard imaging techniques. This is largely attributable to the factthat these shallow junctions do not show up in the cross section scansof an imaging tool, such as a scanning electron microscope (SEM) or atransmission electron microscope (TEM). Thus, it can be very difficultto ascertain with any degree of certainty what structural defects orirregularities might exist in the junction or gate areas of themicroelectronics device.

Accordingly, what is needed in the art is an improved method ofobtaining an image of the junctions areas of a microelectronics device.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, thepresent invention provides a method of imaging a shallow junctionprofile in a microelectronics device. In one embodiment, the methodcomprises cleaning a sample of a microelectronics device to be imagedwith a first solution comprising hydrofluoric acid, an inorganic acidand water, exposing the sample to a second solution comprisinghydrofluoric acid, an inorganic acid and an organic acid, wherein thesecond solution forms a contrast between different regions within thesample, and producing an image of the sample.

In another embodiment, there is provided a method of manufacturing anintegrated circuit. This particular embodiment comprises forming atleast a portion of an integrated circuit on a microelectronic devicesubstrate using a fabrication process and preparing a test sample fromthe portion of the integrated circuit. The test sample is exposed to acontrast solution comprising hydrofluoric acid, an inorganic acid and anorganic acid, wherein the contrasting solution forms a contrast betweendifferent regions within the test sample. An image of the contrastedtest sample is produced to determine if the test sample falls within aspecified parameter. If the test sample falls outside the specifiedparameter, the fabrication process is adjusted to bring an integratedcircuit produced by the fabrication process within the specifiedparameter. The adjusted fabrication process is then used to fabricate anoperative integrated circuit.

The foregoing has outlined preferred and alternative features of thepresent invention so that those of ordinary skill in the art may betterunderstand the detailed description of the invention that follows.Additional features of the invention will be described hereinafter thatform the subject of the claims of the invention. Those skilled in theart should appreciate that they can readily use the disclosed conceptionand specific embodiment as a basis for designing or modifying otherstructures for carrying out the same purposes of the present invention.Those skilled in the art should also realize that such equivalentconstructions do not depart from the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is best understood from the following detailed descriptionwhen read with the accompanying FIGURES. It is emphasized that inaccordance with the standard practice in the semiconductor industry,various features may not be drawn to scale. In fact, the dimensions ofthe various features may be arbitrarily increased or reduced for clarityof discussion. Reference is now made to the following descriptions takenin conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a partial sectional view of microelectronics deviceat an early stage of manufacture and with which the present inventioncan be implemented

FIG. 2 illustrates an image of junction regions of a microelectronicsdevice taken with a transmission electron microscope after beingprepared in accordance with the principles of the present invention;

FIG. 3 illustrates an image of a sample of a microelectronics devicewherein the present invention has not been utilized, thereby showing alack of contrast between the junction regions and the well;

FIG. 4 illustrates an image of a well region of a microelectronicsdevice taken with a scanning electron microscope after being prepared inaccordance with the principles of the present invention; and

FIG. 5 is a partial sectional view of an integrated circuit that can beconstructed using the present invention.

DETAILED DESCRIPTION

Turing initially to FIG. 1, there is illustrated a partial, sectionalview of an exemplary integrated circuit 100 at the first metal levelthat is located over a device level. At this point of manufacture, theintegrated circuit 100 is of conventional design and includes asubstrate 110, such as a microelectronics substrate on which sub-microndevices can be built. The substrate 110 may be configured to serve as awell region for the integrated circuit 100, or it might have anepitaxial layer 115 located thereover in which wells 120 are formed. Thewells 120 may be complementary wells, such as an N-type well and aP-type well, respectively, however, other well known dopingconfigurations are also applicable. The integrated circuit 100 furthercomprises conventional transistors 125, such as complementary NMOS andPMOS transistors, that may include gates 130 and source/drain regions135, 137, respectively. These source/drain regions 135, 137 are oftenreferred to as junctions and can often include lightly doped and haloextensions 138. The spacing between these junctions under the gatedefine the channel length, and this spacing, as well as their dopingprofiles, can have critical implications on the operation of themicroelectronics device 100. As such, it is highly beneficial that thesejunctions be as close to design specifications as possible. Also shownin FIG. 1 are contacts 140, which connect the gates 130 andsource/drains 135, 137 of each of the transistors 125 to overlying metalinterconnect structures 145 formed on an interlevel dielectric layer147.

The present invention provides a unique method for imaging the dopedjunction areas of the microelectronic device 100. In an advantageousembodiment, the sample may be sectioned by using a focused ion beam. Ithas been found that in some cases, the focused ion beam process cancontaminate the sample with gallium. With the present invention, it haspresently been found that contaminants, including gallium, can interferewith or inhibit obtaining a good contrast image of the microelectronicsdevice 100, particularly in the junction region of the device. Thus, inone embodiment, the present invention recognizes the need to remove suchcontaminants from the sample to obtain a high quality image of the crosssection of the microelectronics device 100 for more accurate analysis.It should be understood, however, that in those instances where thesample can be sectioned by methods that significantly reduce suchcontaminants, the removal step may not be necessary.

In those embodiments where contaminants are present, one embodimentcomprises cleaning the sample of the microelectronics device 100 with afirst solution, such as a cleaning solution. The first solutioncomprises a mixture of hydrofluoric acid, an inorganic acid, and water.It should be noted that the sample may be taken from a product line, orit may be a test sample made with the same process used to make theactual product.

The inorganic acid of the first solution is preferably a stronginorganic acid having a pK_(a) of about −1.0 or less. In one embodiment,the inorganic acid is nitric acid. However, in other embodiments, theinorganic acid may be hydrochloric acid, hydrobromic acid, hydroiodicacid, perchloric acid, or sulfuric acid. While, the concentrations ofthe various components of the first solution may vary, it has been foundthat an advantageous solution comprises from about 1 to about 3 parts byvolume of 5% hydrofluoric acid, from about 2 parts to about 4 parts byvolume of 70% strong inorganic acid, and from about 4 parts to about 6parts by volume of water, preferably dionized water. More preferably,the first solution comprises about 2 parts 5% hydrofluoric acid, about 3parts 70% nitric acid and about 5 parts dionizied water. It has beenfound that using the first solution removes contaminants, such asgallium, that are present from the sample, which provides a bettercontrast in the image.

The period of time during which the sample microelectronics device 100is exposed to the first solution may also vary. For example, in oneembodiment, the sample may be placed in the first solution for a periodof time ranging from about 15 seconds to about 20 seconds and at atemperature ranging from about 22 to about 30 degrees centigrade. In amore advantageous embodiment, however, the sample is placed in the firstsolution for about 15 seconds at a temperature of about 22 degreescentigrade.

A contrast solution is used to provide a contrast in the sample of themicroelectronic device 100. The sample, as described below, is placed inthe contrast solution for a period of time. The contrast solution may beused by itself in those instances where the cleaning step is notnecessary to obtain a good image. Alternatively, the contrast solutionmay be used in sequence with the above-discussed first or cleaningsolution. In such instances, the contrast solution is a second solutionin the process. In an exemplary embodiment, the contrast or secondsolution to which the sample is exposed comprises a mixture ofhydrofluoric acid, an inorganic acid, and an organic acid.

The inorganic acid of the contrast or second solution is preferably astrong inorganic acid having a pK_(a) of about −1.0 or less, and theorganic acid is a weak acid having a pK_(a) of about 2.76 or greater. Inone embodiment, the inorganic acid is nitric acid. However, in otherembodiments, the inorganic acid may be hydrochloric acid, hydrobromicacid, hydroiodic acid, perchloric acid, or sulfuric acid. The organicacid, on the other hand, may be, in one embodiment, acetic acid. Inanother embodiment, however, the organic acid may be butonoic acid,formic acid, or propinoic acid. Other organic acids that contain carbonand have the appropriate pK_(a) value are also within the scope of thepresent invention. While, the concentrations of the various componentsof the contrast or second solution may vary, it has been found that anadvantageous solution comprises from about 1 to about 3 parts by volumeof 5% hydrofluoric acid, from about 2 parts to about 4 parts by volumeof 70% strong inorganic acid, and from about 4 parts to about 6 parts of99% organic acid. More preferably, the contrast solution comprises about2 parts 5% hydrofluoric acid, about 3 parts 70% nitric acid and about 5parts 99% acetic acid. It has been found that using the second solutionprovides a much improved image over those previously used and therebyallows for more accurate analysis of the sample, as is shown in thefollowing figures.

The period of time during which the sample microelectronics device 100is exposed to the contrast or second solution may also vary. Forexample, in one embodiment, the sample may be placed in the contrastsolution for a period of time ranging from about 3 seconds to about 16seconds and at a temperature ranging from about 22 to about 30 degreescentigrade. In a more advantageous embodiment, however, the sample isplaced in the contrast or second solution for about 8 second at atemperature of about 22 degrees centigrade.

Following the exposure to the contrast solution, an image of the sampleof the microelectronic device 100 can be taken with an image device,such as a transmission electron microscope (TEM), a scanning electronmicroscope (SEM) or a focused ion beam (FIB) microscope.

Referring now to FIG. 2, there is illustrated an image of amicroelectronics device 200 having junction regions 210, 215, which inthis case are source/drain regions for gates 220, taken with a TEM,after being prepared in accordance with the principles of the presentinvention. In this particular embodiment, the microelectronics device200 was cleaned with the first solution, as discussed above. As seen inthis figure, substantial detail of the junction regions' 210, 215 dopantprofiles are clearly contrasted with the well 217 in which junctionregions 210 and 215 are located and are very visible, including theirrespective lightly doped areas 210 a and 215 a, which define the channellength region 225 of the microelectronics device 200.

Given the amount of detail that is present in this image, a variant ormalformed junction dopant profile or invariant channel length couldeasily be determined. This information could then be used to provide apossible explanation for any deficient operation or qualitative testfailure of the microelectronics device 200. Moreover, the informationobtained from the image could then be used to adjust theout-of-specification fabrication process, such as a dopant implantparameter, to correct the manufacturing problem.

The contrast or second solution, as discussed above, reacts with thedopant and the silicon in the sample to provide the contrast between thejunctions 210 and 215 and the well 217. In essence, the silicon in thedoped junction regions 210 and 215 is substantially or completelyremoved, which provides the contrast between the denser material that isnot significantly affected by the contrast solution and the less densematerial that is so affected. Also, as seen in FIG. 2, the junctions 210and 215 are not the only part of the microelectronics device 200 that isaffected by the solution. In addition, the gate 220 can also be affectedby the solution when doped appropriately. In an advantageous embodiment,the junctions 210 and 215 and the gates 220 are doped with an N-typedopant, such as arsenic. Additionally, while the dopant concentrationmay vary, depending on the design of the microelectronics device 200,the dopant concentration within the junctions 210 and 215 can range fromabout 5E13 atoms/cm³ to about 5E15 atoms/cm³ in an advantageousembodiment. It is believed that the dopant concentration does have aneffect on the quality of the image. For example, if the dopantconcentration is too light, then the contrast solution may not provide agood contrast of the image.

In stark contrast to FIG. 2, FIG. 3 is a TEM image of a microelectronicdevices 300, which include gates 310 and source/drain junctions 315 and320, that was prepared by conventional methods and, therefore, withoutthe benefits provided by the present invention. As seen from this image,there is no contrast between the junction regions 315 and 320 and thewells 325 in which junctions 315 and 320 are formed. As such, this imagecould not be used to determine the possible source of any defect withinthe junction profile or gate regions of the microelectronics devices300. Consequently, it would be extremely difficult, if not impossible,to determine if any particular fabrication process was the source of thedefect.

FIG. 4 illustrates a TEM image of microelectronics device 400 having awell region 410. As seen in this figure, the present invention can alsobe used to contrast the well region 410 so that its dopant profile canbe ascertained. In this particular embodiment, the contrast or secondsolution has caused topographical relief within the well region 410. Thetopographical relief provides the contrast and outlines the profile ofthe well 410. Thus, this can be use in conjunction with the foregoingembodiments to image aspects of a microelectronics device that have notpreviously been easily imaged, and through these images structuralirregularities can be determined and particular fabrication processescan be targeted for adjustment.

FIG. 5 illustrates a partial view of an integrated circuit 500. FIG. 5,briefly illustrates a partial view of an integrated circuit 500. Theintegrated circuit includes transistors 512 of conventional designhaving source/drain junctions 514 and 516, as discussed above. Locatedover the transistors 512 are conventionally formed dielectric layers 524having conventionally formed interconnects 528, such as vias, metallines and contact plugs located therein. The interconnects 528electrically connect the transistors 512 to form an operative integratedcircuit.

The present invention could be used to fabricate the integrated circuit500 in the following way. When a product is produced a test sample ofthat product could be taken and sectioned with a focused ion beam. Thetest sample could then be cleaned, if required, in the manner describedabove. The test sample would then be placed in the contrast or secondsolution to cause contrast regions to form, which would be detectablewith a TEM. If there was an irregularity, for example, in the dopantprofile of the junction region, the doping implantation process could betargeted for adjustment to bring the dopant profile withinspecification. For instance, the dopant profile may be too deep, or itmay extend to far under the gate, thereby causing the channel to be toonarrow, either of which could affect transistor performance. When giventhis information, one skilled in the art could then adjust the implantparameters to correct the structural defects. The adjusted process couldthen be used to fabricate another batch of devices or test samples,which would then be examined using the present invention. If thestructural defects were corrected, then no further adjustments wouldhave to be made to the fabrication process. However, if detectableportions of the microelectronics device continued to be out ofspecification, then further adjustments could be made to the fabricationprocess.

Although the present invention has been described in detail, one ofordinary skill in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thescope of the invention.

1. A method of imaging a junction profile of a microelectronics device,comprising: cleaning a sample of a microelectronics device to be imagedwith a first solution comprising hydrofluoric acid, an inorganic acidand water; exposing the sample to a second solution comprisinghydrofluoric acid, an inorganic acid and an organic acid, the secondsolution forming a contrast between different regions within the sample;and producing an image of the sample.
 2. The method as recited in claim1, wherein the inorganic acid is a strong inorganic acid having a pK_(a)of about −1.0 or less and the organic acid is a weak acid having apK_(a) of about 2.76 or greater.
 3. The method as recited in claim 2wherein the inorganic acid of the first and second solutions is nitricacid and the organic acid is acetic acid.
 4. The method as recited inclaim 2, wherein the inorganic acid is hydrochloric acid, hydrobromicacid, hydroiodic acid, perchloric acid, or sulfuric acid.
 5. The methodas recited in claim 2, wherein the organic acid is butonoic acid, formicacid, or propinoic acid.
 6. The method as recited in claim 1, whereinthe first solution is a solution of from about 1 to about 3 parts byvolume of 5% hydrofluoric acid, from about 2 parts to about 4 parts byvolume of 70% nitric acid, and from about 4 parts to about 6 parts byvolume of water.
 7. The method as recited in claim 6, wherein the secondsolution is a solution of from about 1 part to about 3 parts by volumeof 5% hydrofluoric acid, from about 2 parts to about 4 parts by volumeof 70% nitric acid, and from about 4 parts to about 6 parts by volume of99% acetic acid.
 8. The method as recited in claim 1, wherein cleaningincludes placing the sample into the first solution for a period of timeranging from about 15 seconds to about 20 seconds and at a temperatureranging from about 22 to about 30 degrees centigrade.
 9. The method asrecited in claim 1, wherein exposing includes placing the sample intothe second solution for a period of time ranging from about 3 seconds toabout 16 seconds and at a temperature ranging from about 22 to about 30degrees centigrade.
 10. The method as recited in claim 1, whereinproducing an image includes producing an image of the sample with atransmission electron microscope, a scanning electron microscope or afocused ion beam microscope.